The performance of non-volatile memory systems has improved over the past several years. Changes in technology management have pushed the non-volatile memory devices into cameras, computers, personal data assistants, smart phones, and proprietary business applications.
The current flash memory devices, based on charge storage technologies, have limited life spans due to damage of the charge storage layers during writes. The damage can be caused by physical weakening of the crystal structure used to store the charge. This condition is countered by limiting the number of writes and reads that an individual memory cell can undergo and balancing writes across all of the locations in the memory. The limited reliability of the cells has given rise to error correction strategies and distributed write operations in order to extend the useable life of the memory modules. Many maintenance processes can operate in background without the knowledge of the operator.
Other non-volatile memory technologies are in development that can increase the useable memory density while extending the lifetime reliability of the memory structures. These non-volatile memory technologies include spin transfer torque random access memory (STT-RAM) and resistive random access memory (R-RAM).
The writing process can require significant power to assure the proper data is captured. The data is captured in the cells by an electro-chemical process that forms ion chains in a semiconductor layer. The reaction time and the resulting resistance of the cell can require significant power for a short period. When many cells are written concurrently, the overall power can be a problem.
While the write of the individual cells can be grouped by a byte or word organization, the erase is performed on a block basis. The block erase can simultaneously erase 4K cells. An issue that has arisen in the new R-RAM technology is that the block erase may have insufficient current to reset all of the individual cells in the erase block. Some percentage of the cells can require additional voltage or current in order to switch states. This condition can be caused by the number of written cells in the erase block and the manufacturing distribution of the individual integrated circuit.
In order to verify that all of the individual cells were properly written, a verify read must be performed in order to determine whether all of the individual cells were actually stored the data correctly. This process can lead to iterative write cycles being used to store all of the data. The iterative write cycles can consume additional power and increase background processing time.
Thus, a need still remains for a non-volatile memory system that can reduce the power consumed during a write process while assuring the data is correctly captured. In view of the exponential growth in the use of non-volatile memory in personal electronic devices, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.